In recent years, in general, a photoelectric conversion device has been used as the solid state image-pick up device of a two-dimensional image input device centering on a digital still camera and a video camera recorder or has been utilized as a one-dimensional image reading device centering on a facsimile and a scanner, and has been much in rapid demand.
As the photoelectric conversion device, a CCD (Charge Coupled Device) or MOS type sensor has been used. As a representative of the MOS type sensor, a CMOS photoelectric conversion device (hereinafter referred to as “CMOS sensor”) has been put to practical use (see Japanese Patent Application Laid-Open No. 2001-332714).
FIG. 7 is one example of a circuit block diagram of a solid state image-pick up device mounted with the CMOS sensor.
In FIG. 7, reference numeral 1 a photo diode (hereinafter referred to as [PD]) which converts a light into a signal charge, reference numeral 2 a transfer MOS transistor for transferring a signal charge generated in the PD, reference numeral 3 a floating diffusion region (hereinafter referred to as FD) for temporarily storing a transferred signal charge, reference numeral 4 a reset MOS transistor for resetting the FD3 and PD 1, reference numeral 5 a select MOS transistor for selecting an random line among an array, reference numeral 6 a source follower MOS transistor for converting the voltage of the signal charge of the FD3 and amplifying it by a source follower type amplifier, reference numeral 7 a reading out line which is used in common by a column for reading out a pixel voltage signal, and reference numeral 8 a constant current source for turning the reading out line 7 into a constant current. Although not shown, either or both of a circuit for processing a signal from this pixel and a drive circuit (shift resistor) for driving the transistor in the pixel are formed as a peripheral circuit in the same substrate.
Each pixel (except for the constant current source 8) is disposed in an array pattern, and constitutes an image pick up device.
FIG. 8 is a schematic sectional view of the pixel of the image pick up device mounted with the CMOS sensor, and in particular, it is a view showing a portion of the PD 1 and the transfer MOS transistor 2 in FIG. 7. Reference numeral 11 denotes an n-type silicon substrate, reference numeral 12 a p-type well, reference numeral 13a a gate oxide film of the MOS transistor, reference numeral 13b a thin oxide film on a light receiving portion, reference numeral 14 a gate electrode of the transfer MOS transistor 2, reference numeral 15 an n-type anode of the PD1 (the n-type mode 15 is the same conductivity type as a signal charge and operates to storage and transfer the signal charge), reference numeral 16 a surface p-type region for turning the PD 1 into a berried structure, reference numeral 17 a select oxide film for separating pixels, reference numeral 18 an n-type high concentration region which forms a FD 3 and serves as a drain region of the transfer MOS transistor 2, reference numeral 19 a silicon oxide film for insulating the gate electrode 14 and a metal first layer 21, reference numeral 20 a contact plug, reference numeral 22 an interlayer insulation film for insulating the meal first layer 21 and a metal second layer 23, reference numeral 24 a interlayer insulation layer for insulating the second metal layer 23 and a third metal layer 25, and reference numeral 26 a passivation film. In a color photoelectric conversion device, on the upper layer of the passivation film 26, there are further formed a color filter layer not shown, and also a micro lens for sensitivity improvement. A light incident from the surface passes through an opening portion having no metal third layer 25, and enters the PD. The light is absorbed inside the n-type anode 15 of the PD or the p-type well 12, and generates electron-hole pairs, among which the electrons are stored in the n-type anode 15.
Further, as features of the CMOS sensor, there is cited an advantage of a conventional CMOS process being utilizable, since, in a pixel portion, a PD formation well for forming a light receiving region and a peripheral circuit formation well for forming a drive device are the same conductive type. That is, the utmost features of the CMOS sensor are that, unlike a CCD, no specific production line is required, but that a low cost solid image pick up device can be produced by using an existing semiconductor production line.
FIGS. 11A to 11D and 12A to 12C are views showing each of the well forming methods of the conventional CMOS sensor using an ordinary COMS process.
Here, an example of using the n-type silicon substrate is shown.
First, a silicon thermally oxidized film 27 and a silicon nitride film 28 are formed on the n-type silicon substrate 11 (FIG. 11A).
After removing the silicon nitride film 28 of a desired region by the pattern of a photo resistor 29, a p-type impurity 30 is introduced (FIG. 11B) by ion implantation. After removing the photo resistor 29, when thermally oxidization processing is performed, a silicon oxidized film 31 is formed in the region alone, into which the p-type impurity 30 is introduced. Next, the silicon nitride film 28 is removed, and an n-type impurity 32 is introduced by ion implantation (FIG. 11C). At this time, since there is formed the oxidized film 31 on the region into which the p-type impurity 30 is introduced, the n-type impurity 32 is formed in a region other than the region where the p-type impurity 30 is formed self-align wise. Naturally, the oxidized film 31 is formed by a thick film so as not to be pierced at the implantation time of the n-type impurity 32.
As described above, after introducing the p-type impurity 30 and the n-type impurity 32 into the desired region, a thermo diffusion processing is performed so as to obtain a desired depth and a concentration profile (hereinafter referred to as [impurity profile]), thereby forming a p-type well 12 and an n-type well 33 (FIG. 11D).
Subsequently, after removing all the oxidized films once,
the silicon thermal oxidized film 27 and the silicon nitride film 28 are formed again, and the desired region is subjected to patterning by the photo resistor 29, and the silicon nitride film 28 is subjected to an etching (FIG. 12A).
Finally, after performing electrical isolation by the select oxidized film 17, each well region for forming a MOS transistor, a resistor, a capacitor, a diode and the like is formed (FIG. 12B).
After that, a gate oxidized film 40 and a gate electrode 41 of the MOS transistor are formed, and an n-type region 42 of the PD and a p-type region 43 of the surface are formed, and a source/drain 44 of the NMOS transistor and a source/drain 45 of the PMOS transistor are formed, and after going through a wiring forming process (not shown), the solid state image pick up is completed (FIG. 12C).
Further, FIG. 12B shows from the left in order that a PD forming p-type well, a peripheral circuit p-type well, and a peripheral circuit n-type well are formed by the select oxidized film 17, and there is an advantage of being able to adopt an easy process at a low cost by the minimum photolithographic process and a self-aligning well forming method.
Further, though it is not the conventional CMOS process, as shown in Japanese Patent Application Laid-Open No. 2000-232214, there has been also proposed a method of controlling the impurity profile by providing a buried type epitaxial region in the PD region.
Further, in Japanese Patent Application Laid-Open No. H01-243462, there has been disclosed a solid state image pick up device comprising plural photoelectric conversion pixels and scanning means for reading out a signal of this photoelectric conversion pixel, wherein the photoelectric conversion pixel is formed inside an impurity layer of concentration lower than the impurity layer by which scanning means is formed. This makes it possible to miniaturize a MOS transistor by forming a scanning circuit in a high concentration impurity layer according to a proportion reduction rule. In addition, it has been disclosed that, by forming a photoelectric conversion portion inside a low concentration impurity layer, a depletion layer on the periphery of a photo diode is expanded so as to improve a light sensitivity.
Further, in U.S. Pat. No. 6,445,014, there is a description with regard to a periphery well in which a logical circuit is formed and a well in which a pixel cell is formed. To be more in detail, a constitution is disclosed, wherein the well in which the pixel cell is formed is taken as a retrograde well, and the impurity concentration of the periphery well is reduced from the top toward the bottom of the well (see FIG. 12 of the U.S. Publication). Further, the impurity concentration is 1×1016 to 2×1018 atoms per cm3, and is taken as the same value. Further, with regard to depth of the well to be formed, the well which forms a PD region is deeper (see FIG. 11 of the U.S. Publication).
As described above, though the CMOS solid state image pick up device has an advantage of being able to use the existing CMOS forming manufacturing method, there are some problems involved in order to improve an imaging performance.
A first problem is that the impurity amount to be introduced to the peripheral circuit well region of the same conductive type as the PD well region is made the same as shown in the prior art (FIG. 11B), and for example, in this prior art, the impurity concentrations of the PD well region and the peripheral circuit p-type well region cannot be set separately. For example, to improve spectral characteristics of an incident light, it is not possible to diminish the impurity concentration alone of the PD well nor is it remarkably easy to control a threshold value setting and the like of the MOS transistor provided inside the PD well without changing the concentration of the p-type peripheral circuit well.
A second problem is that the thermal diffusion processing after the introduction of the impurity into each of the PD well region and the peripheral circuit well region is often collectively performed as shown in (FIG. 11D). Hence, it is not possible in principle to control the depth alone of the impurity profile of the PD well region, and so the impurity profile of the peripheral circuit well must be changed each time to improve the characteristics of the CMOS sensor, and this causes a great inconvenience in terms of the design.
Further, according to the constitution disclosed in Japanese Patent Application Laid-Open No. H01-243462, there is a point to be examined as follows. That is, in the constitution where the concentration of the well to form the peripheral circuit is made high, the efficiency of collecting the charge in the photoelectric conversion portion may not be sufficiently achieved. This often grows to a greater problem to be solved as the pixel becomes miniaturized and the sensitivity thereof is reduced.
Further, according to the constitution disclosed in U.S. Pat. No. 6,445,014, there is a point to be examined as follows. That is, though the depth of the well and the structure of the well are made different from the photoelectric conversion well and periphery well, since the impurity concentrations thereof are made the same, as described above, the efficiency of collecting the charge in the photoelectric conversion portion is often not sufficiently achieved.
Hence, an object of the present invention is to provide a photoelectric conversion device able to realize a PD well structure, which contributes to the improvement of an imaging performance, while using the existing CMOS manufacturing method.